The present invention is generally related to integrated circuit packaging, and more particularly, relates to methods and devices for providing compliant packaging for integrated circuits.
The manufacturing process of an integrated circuit (IC) part can be summarized by the following three steps: I) IC fabrication, II) IC packaging, and III) IC testing. The IC fabrication, further classified into front-end and back-end processing, refers to the fabrication of the transistors and metal levels on the ICs in wafer form at the semiconductor foundry. The IC packaging involves packaging the IC to protect, power, and cool the IC and also provide electrical and mechanical connections between the IC and the outside world. The IC packaging is typically accomplished at a packaging foundry separate from the semiconductor foundry. Multiple testing protocols are used from the bare wafer state to fully fabricated and packaged IC state. Therefore, the IC testing involves both the semiconductor and the package foundries. In conventional electronic assembly, the wafer is subjected to simple testing procedures to identify functioning and non-functioning ICs at the end of the IC fabrication process. The wafer is then diced into individual ICs. The functional ICs are shipped to the package foundry to complete the package assembly process. The package assembly process begins at the package foundry where each IC goes through series of steps. The IC is first placed in a temporary package for electrical and reliability test and burn-in. Good ICs are disassembled from the temporary package and placed into a permanent package. Each package is tested once more for functionality before it is approved for system assembly. The package assembly and testing procedures beyond wafer scribing involve one IC at-a-time, significantly increasing the cost of producing the packaged IC.
As well, these packaged ICs are generally incorporated into electronic devices by mounting the ICs on substrates, such as printed wiring boards (PWBs). These PWBs physically support and electrically connect the ICs to other elements in the circuit. The structures utilized to connect the IC to the substrate accommodate the electrical and mechanical interconnections to the chip and are commonly referred to as input/output connections (I/O). Normally, these I/O connections are subject to substantial stresses due to the thermal cycling as the temperatures within the electrical device cycle during operation. For example, electrical power dissipated during operation tends to heat up both the substrate and the associated IC, then both the IC and substrate cool as power is secured to the electrical device. In that the substrate and the IC are generally constructed of different materials having different coefficients of thermal expansion, the IC and substrate will expand and contract by different amounts and at different rates. This motion of the IC relative to the substrate can cause movement of the I/O connections and place them under mechanical stress. Repeated occurrence of these stresses may cause breakage of the I/O connections and ultimate failure of the IC.
Thus, heretofore unaddressed needs exist in the industry to address the aforementioned deficiencies and inadequacies.
The present invention provides an apparatus and method for producing compliant wafer level packages.
Briefly described, one aspect the present apparatus can be described as a monolithically fabricated compliant wafer level package (CWLP) for packaging electronic devices, having a compliant layer with a first surface parallel to a second surface, and a compliant interconnect passing between the first surface and the second surface of the compliant layer. The compliant interconnects being provided so that electrical and mechanical connections may be supported across the compliant layer. Preferably, the compliant interconnect further comprises a substantially vertical portion and a portion that is substantially horizontal to the first surface and the second surface of the compliant level, thereby accommodating relative motion between elements disposed on opposing sides of the compliant layer, yet electrically and mechanically connected by the compliant interconnect.
The present invention can also be viewed as providing a method for monolithically fabricating compliant wafer level packages. In this regard, the method can be broadly summarized by providing a substrate having a compliant layer on a first side, the compliant layer having a via that exposes a die pad along the first side of the substrate, and fabricating a compliant interconnect so that a first end of the compliant interconnect contacts the die pad. In fabricating the compliant interconnect, further optional but preferred steps include providing a substantially vertical portion of the compliant interconnect contacting the die pad and providing a substantially horizontal portion of the compliant interconnect that contacts the upper surface of the compliant layer.
Other systems, methods, features, and advantages of the present invention will be or become apparent to one with skill in the art upon examination of the following drawings and detailed description. It is intended that all such additional systems, methods, features, and advantages be included within this description, be within the scope of the present invention, and be protected by the accompanying claims.